1. Field of the Invention
The invention relates to a digital data sampling circuit. In particular, the invention relates to a shift register structure of the low-power digital data sampling circuit in a display panel.
2. Description of the Related Art
FIG. 1 shows digital data DATA transmitting and sampling in a conventional liquid crystal display. Digital data DATA through interface circuit 12 and delay buffers 14 is transmitted to each sample latch circuit 16 serially. Shift register 18 provides control signals (SP1, SP2, SP3 . . . SP(n−1), SPn) serially to trigger each sample latch circuit 16 serially. Thus each sample latch circuit 16 serially samples digital data DATA. In a conventional digital data sampling circuit, digital data DATA arrives at sample latch circuit 16 earlier than control signals (SP1, SP2, SP3 . . . SP(n−1), SPn). Therefore, a plurality of delay buffers 14 are used to delay digital data DATA for synchronizing control signals (SP1, SP2, SP3 . . . SP(n−1), SPn) and digital data DATA received by sample latch circuit 16.
FIG. 2 is timing diagram illustrate digital data DATA and control signals (SP1, SP2, SP3 . . . SP(−1), SPn) of the conventional liquid crystal displays. Because of delay buffers 14, control signals (SP1, SP2, SP3 . . . SP(n−1), SPn) and digital data DATA will arrive at sample latch circuit 16 in the same time. In FIG. 2, when start pulse horizontal signal STH is at high voltage level and clock horizontal signal CKH is triggered to high voltage level, first output signal OUT1 is triggered to high voltage level. When clock horizontal signal CKH switches to low voltage level, second output signal OUT2 is triggered to high voltage level. In addition, first control signal SP1 is the logical AND result of first output signal OUT1 and second output signal OUT2. Thus, when first output signal OUT1 and second output signal OUT2 both are at high voltage level, first control signal SP1 is at high voltage level. When start pulse horizontal signal STH is at low voltage level and clock horizontal signal CKH is also triggered to high voltage level, first output signal OUT1 switches to low voltage level. At the same time, first control signal SP1 also switches to low voltage level. Second control signal SP2 immediately switches to high voltage level after first control signal SP1 switches to low voltage level. Third control signal SP3 is also triggered to high voltage level immediately after second control signal SP2 switches to low voltage level. Each control signal (SP1, SP2, SP3 . . . SP(n−1), SPn) serially transmits to each sample latch circuit 16.
The conventional technology uses a plurality of delay buffers 14 to synchronize control signals (SP1, SP2, SP3 . . . SP(n−1), SPn) and digital data DATA received by sample latch circuit 16. However, delay buffers 14 would consume considerable power and increase costs or layout area. As transmission speed of digital data DATA increases, the power consumption for data transmission is also increased.